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System-level software performance simulation considering out-of-order processor execution

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3 Author(s)
Roman Plyaskin ; Institute for Integrated Systems, Technische Universität München, Arcisstr. 21, 80290 Munich, Germany ; Thomas Wild ; Andreas Herkersdorf

Host-compiled software simulation has become a popular method to accelerate iterative system-level design space explorations of multiprocessor systems-on-chip (MPSoCs) by abstracting the internal microarchitecture of cores. However, current approaches do not consider out-of-order processor architectures, which are emerging in the embedded system domain. Out-of-order processors exhibit complex timing behavior which is difficult to model at a high level of abstraction. In this paper, we improve the accuracy of compiled simulations for out-of-order processors. Our method is applied to binary-level compiled simulation of the target code. We discuss how to annotate timing in the target code and consider out-of-order effects at run-time of the compiled simulation. The proposed approach allows for reproducing the system-level timing behavior of an out-of-order processor observed in a cycle-accurate simulator on average 25× faster at an average error of 3%.

Published in:

System on Chip (SoC), 2012 International Symposium on

Date of Conference:

10-12 Oct. 2012