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Power double-diffusion metal-oxide-semiconductor (DMOS) transistors are often subject to significant self-heating and, thus, high device temperatures. This limits their safe operating area and reliability. Hence, a certain minimum device area is usually required for sufficient heat dissipation. However, this area often exceeds the on-state resistance requirements for advanced technologies. Thus, accurate modeling of DMOS device temperatures is crucial to avoid oversizing and to fully exploit the potential of modern technologies. In this paper, we present a modeling and simulation approach that can be used to predict the device temperature up to thermal runaway. For this, we introduce a 3-D numerical simulator which accounts for the coupled electrothermal behavior in a computationally efficient way, allowing the simulation of typical power transistors in only a few minutes. Furthermore, we will discuss how the temperature-dependent DMOS transistor behavior can be modeled for our simulations up to extremely high temperatures by extrapolation from characterization data limited to 300°C. Our approach has been successfully verified experimentally for device temperatures exceeding 500°C up to the onset of thermal runaway. Measurement and simulation results will be presented for both vertical and lateral DMOS transistors fabricated in two automotive BCD technologies.