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VLSI Architectures for the 4-Tap and 6-Tap 2-D Daubechies Wavelet Filters Using Algebraic Integers

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5 Author(s)
Madishetty, S.K. ; Dept. of Electr. & Comput. Eng., Univ. of Akron, Akron, OH, USA ; Madanayake, A. ; Cintra, R.J. ; Dimitrov, V.S.
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This paper proposes a novel algebraic integer (AI) based multi-encoding of Daubechies-4 and -6 2-D wavelet filters having error-free integer-based computation. Digital VLSI architectures employing parallel channels are proposed, physically realized and tested. The multi-encoded AI framework allows a multiplication-free and computationally accurate architecture. It also guarantees a noise-free computation throughput the multi-level multi-rate 2-D filtering operation. A single final reconstruction step (FRS) furnishes filtered and down-sampled image outputs in fixed-point, resulting in low levels of quantization noise. Comparisons are provided between Daubechies-4 and -6 designs in terms of SNR, PSNR, hardware structure, and power consumptions, for different word lengths. SNR and PSNR improvements of approximately 30% were observed in favour of AI-based systems, when compared to 8-bit fixed-point schemes (six fractional bits). Further, FRS designs based on canonical signed digit representation and on expansion factors are proposed. The Daubechies-4 and -6 4-level VLSI architectures are prototyped on a Xilinx Virtex-6 vcx240t-1ff1156 FPGA device at 282 MHz and 146 MHz, respectively, with dynamic power consumption of 164 mW and 339 mW, respectively, and verified on FPGA chip using an ML605 platform.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:60 ,  Issue: 6 )