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Flying-Adder Fractional Divider Based Integer-N PLL: 2nd Generation FAPLL as On-Chip Frequency Generator for SoC

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3 Author(s)
Liming Xiu ; Kairos Microsyst. Corp., Plano, TX, USA ; Win-Ting Lin ; Tsung-Ta Lee

Flying-Adder direct period synthesis is a technology that directly constructs output clock period from a known base time unit Δ. In the past, it is mainly used for driving digital load. In this work, a new scheme is proposed to produce spectrally pure clock signal at certain frequencies which can be used to drive devices such as SoC on-chip ADC, DAC and etc. This scheme utilizes a Flying-Adder synthesizer as a fractional divider placed inside the PLL loop. Additionally, a PDFR technique is used to help improve the frequency resolution. Moreover, a unique accumulator is used to boost circuit speed. A 55 nm implementation is fabricated and is used to validate the architecture of this 2nd generation Flying-Adder PLL. The resolution of this enhanced integer-N PLL is 1.5 MHz across the entire VCO operating range with a 12 MHz input and loop bandwidth of 1 MHz. The power consumed is 8.3 mW at 2.3 GHz and the area is 0.16 mm2 . The significance of this fractional divider is discussed at the end. A brief comparison between this clock generator and others is given at the end as well.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:48 ,  Issue: 2 )

Date of Publication:

Feb. 2013

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