We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

SSC-a tool for the synthesis of testable sequential machines

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Makki, R.Z. ; North Carolina Univ., Charlotte, NC, USA ; Muha, J. ; Boughazale, S. ; Kaylani, T.

A new CAD system, called SSC, is presented for the design and test of finite-state machines (FSMs). SSC utilizes a controlled design environment to simplify the logic synthesis and verification process. SSC utilizes a high-level structured input description where the state sequencing information is implicit in the specification. It is demonstrated that synthesis for testability and test generation depend on the type of state assignment adopted. SSC offers flexibility of choice in the synthesis of FSMs. It is shown that this flexibility is important because each of the state assignment options in SSC is tailored for a specific FSM structure. This enhances the performance of the final product as measured by silicon area, speed, and testability.<>

Published in:

Compcon Spring '90. Intellectual Leverage. Digest of Papers. Thirty-Fifth IEEE Computer Society International Conference.

Date of Conference:

Feb. 26 1990-March 2 1990