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A one-transistor-synapse strategy for electrically-programmable massively-parallel analog array processors

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4 Author(s)
Dominguez-Castro, R. ; Inst. de Microelectron., Seville Univ., Spain ; Espejo, S. ; Rodriguez-Vazquez, A. ; Carmona, R.

This paper presents a linear, four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area occupation and power dissipation of the basic processing units. This allows higher integration densities and therefore, permits the integration of larger arrays on a single chip

Published in:

Analog and Mixed IC Design, 1997. Proceedings., 1997 2nd IEEE-CAS Region 8 Workshop on

Date of Conference:

12-13 Sep 1997