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Quick design of high-performance ΣΔ modulators using CAD tools: a 16.4 b 1.71 mW CMOS ΣΔM for 9.6 ksample/s A/D conversion

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4 Author(s)
Medeiro, F. ; Inst. de Microelectronica, Seville Univ., Spain ; Perez-Verdu, B. ; de la Rosa, J.M. ; Rodriguez-Vazquez, A.

The possibility of using CAD tools to produce high-performance ΣΔ modulator (ΣΔM) ICs is illustrated in this paper through the design of a low-power 2nd-order ΣΔM. It is intended to be used in the front-end of a CMOS 0.7 μm energy metering ASIC. The fabricated prototype features 16.4-b dynamic range (DR) for 9.6-ksample/s output rate with a power budget of 1.71 mW. Such performance places this ΣΔM IC between those reported up to now with lowest value of the Power(W)/2resolution(bit)×Output Rate(Hz) figure

Published in:

Analog and Mixed IC Design, 1997. Proceedings., 1997 2nd IEEE-CAS Region 8 Workshop on

Date of Conference:

12-13 Sep 1997