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IBM second-generation RISC machine organization

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13 Author(s)

A highly concurrent second-generation superscalar reduced-instruction-set computer (RISC) is described. It combines a powerful RISC architecture with sophisticated hardware design techniques to achieve a short cycle time and a low cycles-per-instruction (CPI) ratio. Like earlier RISC processors, this design employs a register-oriented instruction set, the CPU is hardwired rather than microcoded, and it features a pipelined implementation. Unlike earlier RISC processors, several advanced architectural and implementation features are employed. They include separate instruction and data caches, zero-cycle branches, multiple-instruction dispatch, and simultaneous execution of fixed- and floating-point instructions. The CPU has a four-word data bus to main memory, a four-word instruction-fetch bus from the I-cache arrays, and a two-word data bus between the D-cache and floating-point unit. These provide the high instruction and data bandwidths required for a high-performance superscalar implementation.<>

Published in:

Compcon Spring '90. Intellectual Leverage. Digest of Papers. Thirty-Fifth IEEE Computer Society International Conference.

Date of Conference:

Feb. 26 1990-March 2 1990

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