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High performance issue oriented architecture

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5 Author(s)
Bhandarkar, D. ; Digital Equipment Corp., Boxborough, MA, USA ; Orbits, D. ; Witek, R. ; Cardoza, W.
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An issue-oriented architecture designed for high performance is described. It uses features, such as simple instruction formats, large number of registers, and load/store architecture, found in some reduced-instruction-set-computer architectures. It also includes features, such as out-of-order completion, imprecise exceptions, and vector processing, found in supercomputers such as the CRAY-1. Furthermore, it provides a full set of system support features, such as multiprocessor synchronization, vectored exceptions, stacks, asynchronous system traps, and extensive memory management, found in complex architectures such as the VAX. The reduced instruction parallel/pipelined (RIP) architecture is described. The RIP architecture was designed as a robust architecture to meet a wide range of system requirements across a family of implementations. The processor model that guided the architecture definition consists of multiple pipelined function units, each of which executes a class of instructions.<>

Published in:

Compcon Spring '90. Intellectual Leverage. Digest of Papers. Thirty-Fifth IEEE Computer Society International Conference.

Date of Conference:

Feb. 26 1990-March 2 1990