By Topic

Integrated Power and Clock Distribution Network

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Seyed E. Esmaeili ; Department of Electrical and Computer Engineering, Concordia University, Montreal, Canada ; Asim J. Al-Kahlili

In this brief, we investigate and propose solutions for integrating the clock and power distribution networks all the way to circuit level. The aim is to reduce metal requirements, routing complexity, and power. The concept of an integrated power and clock distribution network (IPCDN) is proposed in order to eliminate the need for the global and local clock distribution networks. In IPCDN, a differential power-clock signal (Pwr_Clk) with a suitable dc voltage level and sinusoidal voltage-swing feeds the VDD ports in combinational and sequential elements. A clock buffer is used for sequential elements in order to extract a full-swing clock from the differential Pwr_Clk+ and Pwr_Clk- signals. IPCDN does not require any change to be made to the conventional combinational and sequential circuit design. The proposed elements of IPCDN, including the LC differential Pwr_Clk driver and the clock buffer, have been simulated using Taiwan Semiconductor Manufacturing Company 65-nm CMOS technology with a Pwr_Clk signal, a 1-V dc component, and 400-mV sinusoidal swing at a frequency of 5 GHz. In addition, the behavior of a master-slave flip-flop with IPCDN was investigated at extreme corners. Simulation results demonstrate correct functionality of all elements of the IPCDN. Comparing IPCDN to a buffered square-wave clock distribution network illustrates that, with a heavily loaded network, IPCDN achieves around 20% reduction in power. This percentage increases when the network capacitance is dominating.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:21 ,  Issue: 10 )