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State-of-the-art compact models of gate access resistance are investigated and compared with RF measurements for 28-nm high-k/metal gate MOS transistors. This work shows that the usual lumped gate resistance model fails to capture both geometry scaling and voltage dependence observed on silicon. The increasing role of the interface resistance is highlighted, and an improved gate access resistance model is proposed, featuring an encapsulation of the interface resistance component by parasitic capacitances. Theoretical insights and relevance of this new distributed model and associated parameters are also discussed.