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The Epsilon-2 hybrid dataflow architecture

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2 Author(s)
Grafe, V.G. ; Sandia Nat. Lab., Albuquerque, NM, USA ; Hoch, J.E.

Epsilon-2 is a general parallel computer architecture that combines the fine-grain parallelism of dataflow computing with the sequential efficiency common to von Neumann computing. Instruction-level synchronization, single-cycle context switches, and reduced-instruction-set-computer-like sequential efficiency are all supported in Epsilon-2. Epsilon-2 is based on an intrinsically parallel computation model. The instruction scheduling model of Epsilon-2 is a generalization of both the von Neumann and dataflow models. The storage model of Epsilon-2 is a parallel generalization of a traditional stack-based storage model. The system is built around a module consisting of a processor board and structure memory board, connected by a four-by-four crossbar, an input/output port, and the global interconnect. In this way, each additional unit of processing brings with it a unit of structure memory, a unit of I/O bandwidth, and a unit of global interconnect bandwidth. A sample code is presented in detail, and the progress of the physical implementation discussed.<>

Published in:

Compcon Spring '90. Intellectual Leverage. Digest of Papers. Thirty-Fifth IEEE Computer Society International Conference.

Date of Conference:

Feb. 26 1990-March 2 1990

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