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Novel Design Method for Electrically Symmetric High-Q Inductor Fabricated Using Wafer-Level CSP Technology

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3 Author(s)
Yutaka Aoki ; CASIO Comput. Co., Ltd., Tokyo, Japan ; Shoichi Shimizu ; Kazuhiko Honjo

High-Q spiral inductors are described that are embedded in the wafer-level chip-size package (WLP) and suffer from unfavorable two-port asymmetric characteristics. To solve this problem, a novel clip-type inductor is proposed, where an electrode crossover point in multiturn inductor structures is modified from a conventional mirror symmetric point to a novel electrical symmetric point. These novel clip-type inductors are designed and fabricated using the WLP technology. By means of a developed 4 nH novel clip inductor, a Q factor value difference between the two ports can be significantly reduced to 1.4% from 14.8% at 1.4 GHz. The Q factors of developed inductors are evaluated under both a conventional short-circuited load condition and an impedance-matched condition. In addition, a novel evaluation method for inductance values for inductors is also described. By using newly derived formulas, inductance values for a fabricated WLP clip-type inductor and a fabricated meander-type inductor are evaluated. This method represents the inherent nature of inductor devices under test including circuit parasitic elements.

Published in:

IEEE Transactions on Components, Packaging and Manufacturing Technology  (Volume:3 ,  Issue: 1 )