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Motion estimation in H.264/AVC, is done in two parts - integer-pel motion estimation, and fractional-pel motion estimation. In the past, we have proposed new algorithms and architectures for integer-pel motion estimation. In this paper, we propose an efficient, low power algorithm and its co-designed VLSI architecture for fractional-pel motion estimation in H.264/AVC. We use a simplified FIR filter for half-pel interpolation. Usage of this filter reduces the required number of computations and the memory size and bandwidth for half-pel interpolation. Simulations are used to compare our algorithm with the state-of-the-art, in terms of rate-distortion performance and computational complexity. Our results show that our algorithm on average has better rate-distortion performance, compared to previous state-of-the-art fractional-pel ME algorithms, while its performance is comparable to fractional-pel ME in H.264/AVC.