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Designing a VAX for high performance

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2 Author(s)
Fossum, T. ; Digital Equipment Corp., Boxborough, MA, USA ; Fite, D.B., Jr.

The strategy used by the designers to achieve the high performance of the VAX 9000 is described. The strategy chosen was to apply reduced-instruction-set-computer-like techniques in implementing the VAX architecture. VAX instructions were broken into small, simple tasks, and dedicated hardware optimized for each task was designed. The result is a network of specialized processors, operating in parallel, executing instructions quickly. The most common, simple instructions are executed at the rate of 1/cycle. To increase system performance further, a high-density, high-speed technology was specifically developed for the VAX 9000. Emitter-coupled-logic (ECL) macrocell arrays (MCA3s), high-density signal carriers (HDSCs), and multichip units (MCUs) allow efficient use of limited physical area. The VAX 9000 scalar and vector processors reside on a single planar board. Three MCU slots are reserved for the optional VBOX vector processor. Integrating the vector processor directly with the scalar processor kept critical interconnects short, reducing vector instruction overhead.<>

Published in:

Compcon Spring '90. Intellectual Leverage. Digest of Papers. Thirty-Fifth IEEE Computer Society International Conference.

Date of Conference:

Feb. 26 1990-March 2 1990