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The CRAY Y-MP: a user's viewpoint

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2 Author(s)
Stevens, K.G., Jr. ; NASA Ames Res. Center, Moffett Field, CA, USA ; Sykora, R.

The significant hardware and software aspects of the first CRAY Y-MP system to be delivered are described. Performance comparisons are made with other Cray products, and the overall system configuration into which the CRAY Y-MP was integrated are described. The CRAY Y-MP mainframe has eight CPU modules implemented with 2500-gate macrocell array logic chips and 32 memory modules made with the same logic chips and with emitter-coupled-logic-compatible RAM chips. A 1.56-billion-operations-per-second speed was achieved for a general sparse matrix factorization algorithm, which was applied to solve the statics problem for several large-scale finite-element models. It has demonstrated an availability of 96.8%. The multiprocessing tools provided with the system and the system performance and configuration are discussed.<>

Published in:

Compcon Spring '90. Intellectual Leverage. Digest of Papers. Thirty-Fifth IEEE Computer Society International Conference.

Date of Conference:

Feb. 26 1990-March 2 1990

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