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A fully integrated high power density capacitive 2:1 step-down DC-DC converter is designed in a standard CMOS technology. The converter implements the presented flying well technique and intrinsic charge recycling technique to deliver a maximum output power of 1.65 W on a chip area of 2.14 mm2, resulting in a power conversion density of 0.77 W/mm2 . A peak power conversion efficiency of 69% is achieved, leading to an efficiency enhancement factor of +36% with respect to a linear regulator. This is for a voltage step-down conversion from twice the nominal supply voltage of a 90 nm technology (2Vdd = 2.4 V) to 1 V.
Date of Publication: Sept. 2013