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Investigation of gate-induced drain leakage (GIDL) in thick-oxide dual-gate doped- and undoped-channel FinFET devices through 3-D process and device simulations is presented. For a given gate length (LG) and gate dielectric thickness, the placement and grading of the drain junction and the channel doping are shown to have a tremendous impact on GIDL. Suppression of GIDL by as much as two orders of magnitude can be realized by formation of steep underlapped junctions for both doped- and undoped-channel devices. The prospect of low leakage levels in doped-channel high- VT FinFETs makes them suitable for memory cell applications.