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In the present investigation, Rijindael's encryption algorithm (AES) is designed based on co-design methodology. It is a commonly used network security algorithm for wireless transmission systems. It is a symmetric block cipher, which plays a major role in bulk data encryption. Four different modules with specific functions are included in this algorithm. The hardware / software co-design methodology is adopted to implement one of the functional modules in hardware and subsequent remaining modules in software. The module in hardware is implemented on FPGA and added as hardware accelerator to the processor. The proposed hardware / software implementation is done on Altera NIOS II processor platform. An implementation result shows a considerable improvement in speed as compared to software only approach. On the other hand, the significant reduction in area is achieved as compared to hardware only approach.