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1Time to market becomes a critical constraint in the context of increase in size and complexity of embedded system design. The paper presents a methodology for the interface of any custom hardware with the system designed around a soft core processor through general purpose input and output (GPIO). The custom hardware under consideration is Advanced Encryption Standard Algorithm (AES). An `AES,' is a standard encryption algorithm used in many security networks for transmission of data. The algorithm is written in `VHDL,' and is interfaced with the processor by custom peripherals. The `NIOS II' soft core processor is used to ensure the flexibility and ease of custom hardware interface. The system is designed using `SOPC' builder tool in `ALTERA'. An `AES,' is interfaced with the system using `GPIO' and the control part is implemented in software in `NIOS II' integrated development environment (IDE). The implementation is done on `Cyclone II FPGA' kit. In the present investigation, based on performance results it is verified that the implementation of `AES' as a `custom hardware,' facilitates the considerable reduction in thermal power dissipation in comparison with implementation in hardware. However, in comparison with implementation in software, `AES' as a `custom hardware,' accelerates the system.