By Topic

Curriculum design using mentor graphics higher education program (HEP) for ASIC Designing from synthesizable HDL to GDSII

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Muhammad Kamran Bhatti ; Department of Graduate Studies and Applied Sciences, Bahria University, Islamabad, Pakistan ; Abid Ali Minhas ; Muhammad Najam-ul-Islam ; Muhammad Adnan Bhatti
more authors

Excellent curriculum design plays pivotal role in the better understanding of theoretical concepts. A curriculum for Application Specific Integrated Circuit (ASIC) design using Mentor Graphics Higher Education Program (HEP) is presented in this paper. To enhance the strength in-depth learning, Design for Test (DFT) has also been embedded in the curriculum design. This enables an extra level of testability feature in educational environment. The main objective of the curriculum is to correlate the theoretical knowledge with practical understanding through hands-on lab sessions which increase the interest of students in the field of ASIC design. Therefore, the lab session that covers the practical side of theoretical material discussed in course is designed specially to incorporate the use of theoretical knowledge with practical understanding. The designed course overcomes the lack of understanding of synthesizable and non-synthesizable Hardware Description Language (HDL) for ASIC design and implementation which is the most important thing for ASICs. The curriculum is developed for duration of 18 weeks so that the students learn the ASIC design flow including advanced tools ModelSim®, Leonardo SpectrumTM, DFT AdvisorTM, Design Architect®-IC, Eldo®, EZ-wave®, IC-Station® and Calibre®. The syllabus is proposed for Mentor Graphics HEP Curriculum in which students are assigned projects so that at first they can learn the difference between synthesizable and non-synthesizable HDL for ASIC and then explore the Design for test feature down to physical layout design and its verification. Some key issues regarding ASIC design are also addressed in this curriculum so that students can visualize the important parameters to be considered in ASICs. The proposed curriculum has been implemented on a sample of students and very promising results are achieved.

Published in:

Teaching, Assessment and Learning for Engineering (TALE), 2012 IEEE International Conference on

Date of Conference:

20-23 Aug. 2012