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A New Reliability Evaluation Methodology With Application to Lifetime Oriented Circuit Design

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2 Author(s)
Sajjadi-Kia, H. ; Dept. of Electr. & Comput. Eng., North Dakota State Univ., Fargo, ND, USA ; Ababei, C.

We propose a new circuit-level vulnerability and reliability evaluation methodology and utilize it to develop a lifetime aware floorplanning strategy. Our work is motivated by increasingly adverse aging failure mechanisms, which have made reliability a growing fundamental challenge in the design of integrated circuits. Because the proposed methodology is based on a divide-and-conquer approach, it enjoys the benefits of transistor level accuracy and of block-level efficiency. At the core of the lifetime estimation engine lies a Monte Carlo algorithm which works with failure times modeled as Weibull and lognormal distributions for several aging mechanisms including time-dependent dielectric breakdown, negative bias temperature instability, electromigration, thermal cycling, and stress migration. To demonstrate the value of the proposed reliability evaluation methodology and floorplanning strategy, we apply them to a network-on-chip router design example. The new floorplanning approach is able to find floorplans with up to 15% difference in the lifetime of the router design. In addition, the proposed reliability evaluation methodology identifies the routing computation and virtual channel allocation units as the most vulnerable subblocks of the design. Such information can be very useful to designers to predict circuit and system mean time to failure and to focus on cost-effective design techniques targeted at specific parts of the design to improve its lifetime.

Published in:

Device and Materials Reliability, IEEE Transactions on  (Volume:13 ,  Issue: 1 )