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The through-silicon-via (TSV) interposer is expected to be the driving vehicle for 2.5-D integrated circuit integration. Although a number of studies have been reported on the thermo-mechanical reliability of TSVs, it remains difficult to justify whether a TSV design or an interposer design is manufacturable or not because we still lack experimental reliability data. This investigation provides important experimental data as well as a series of correlation studies by finite element (FE) simulations. A 2-D analytical solution is also examined to help understand the physics of the problem. Regarding the experimental results, wafer cracking is observed for TSV arrays with large diameters and small pitch-to-diameter ratios after annealing at 300°C. The critical strength to wafer cracking is determined to be 388 MPa from some FE analyses. Through analytical considerations, the influence of TSV diameter on wafer cracking is found to rely on the contributions from the dielectric layer thickness and also the barrier layer thickness. An empirical model for the design of copper-filled TSV interposers is ultimately generated based on the modification of the 2-D solution.