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On-chip Communication Buffer Architecture Optimization Considering Bus Width

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4 Author(s)
Sombatsiri, S. ; Grad. Sch. of Inf. Sci. & Technol., Osaka Univ., Suita, Japan ; Sakanushi, K. ; Takeuchi, Y. ; Imai, M.

This paper studies the on-chip communication buffer optimization method for design space exploration, considering bus width. For embedded multicore system-on-a-chip (MCSoC), there usually are many buses on the system to handle a vast amount of data communications between several processing cores. Therefore, buffer architecture optimization has become one of the most important topics in this area as a parameter for communication architecture. This paper proposes an SRAM optimization method to construct buffer architecture candidates through architecture exploration. Moreover, the design quality of each system architecture candidate is evaluated. The experiment of the proposed method is applied to a JPEG encoder system. The result shows that the proposed exploration method can explore a variety of buffer architecture with trade-off between transfer time and area. Moreover, the result shows that buffer architecture optimization through exploration with pruning can reduce the computation time by approximately 94%.

Published in:

Embedded Multicore Socs (MCSoC), 2012 IEEE 6th International Symposium on

Date of Conference:

20-22 Sept. 2012

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