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Efficient integrated AES crypto-processor architecture for 8-bit stream cipher

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2 Author(s)
Ahmad, N. ; Center for Res. in Analog & VLSI Microsyst. Design, Massey Univ., Auckland, New Zealand ; Rezaul Hasan, S.M.

Adoption of the Advanced Encryption Standard (AES) as a symmetric encryption algorithm for numerous applications requires a low cost and low power design. Presented is a new 8-bit stream cipher architecture core for an application specific integrated circuit AES crypto-processor. The chip area and power are optimised along with high throughput. It is implemented in a 130nm CMOS process and supports both encryption and decryption using 128-bit keys with a throughput of 0.05 Gbit/s (at 100 MHz clock). This design utilises 3152 gate equivalents including an on-the-fly key scheduling unit along with 4.23 W/MHz power consumption. Compared to other 8-bit implementations, the proposed design achieves a smaller chip size along with higher throughput and lower power dissipation.

Published in:

Electronics Letters  (Volume:48 ,  Issue: 23 )