Insights in the Physical Damage of $V_{\rm GS} = V_{\rm DS}$ High-K PMOSFET Degradation in AC Switching Conditions

In this paper, the device degradation enhanced by localized drain self-heating (LDSH) effects at
$V_{\rm GS} = V_{\rm DS}$
bias condition has been measured and characterized in the pMOSFET transistors of an advanced CMOS HKMG 28-nm bulk technology in both dc (constant voltage) and ac (rectangular pulse) conditions. A comparison with the pMOSFET aging during symmetric
$(V_{\rm DS} = \hbox{0}\ \hbox{V})$
negative bias temperature instability (NBTI) condition gives experimental evidence that the physical damage generated at
$V_{\rm GS} = V_{\rm DS}$
bias conditions is dominated by the quasi-permanent component of a symmetric “NBTI-like” thermally activated process with an effective temperature determined by LDSH effects dominating during switching. Similar to conductive
$(V_{\rm GS} \approx \hbox{1/2}V_{\rm DS})$
hot carrier phenomena, a quasi-static approximation can be assumed for the
$V_{\rm GS} = V_{ \rm DS}$
condition during ac switching. In this case, however, the device damage relates to the NBTI response to the effective temperature profile reached during the
$V_{\rm GS} \approx V_{\rm DS}$
transients as well as the relation of the associated duty cycles to the values of the LDSH thermal time constants at the stress conditions. The obtained results clearly show that end-of-life projections using dc models will greatly overpredict the level of
$V_{\rm GS} = V_{\rm DS}$
degradation expected in typical digital applications. On the contrary, our study provides experimental evidence that the
$V_{\rm GS} = V_{\rm DS}$
bias condition is not expected to contribute to device aging during typical digital switching frequencies
$(f \approx \hbox{GHz})$
and brings further light on the physical mechanism responsible for its observed reduced sensitivity from dc to ac.