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Ultralow-k dielectric materials generally show weak mechanical strength (E <; 8 GPa), a high coefficient of thermal expansion (5 ppm/°C-8 ppm/°C), and poor adhesion ( <; 5 J/m2-10 J/m2). As a result, ultralow-k delamination becomes a major failure mode after the packaging reliability test. This paper investigates the propagation mechanism of ultralow-k delamination during the temperature cycling test (TCT). A full understanding this delamination processes is critical for selecting an adequate underfill and protecting both the ultralow-k chip and the lead-free solder bump. This paper shows that the ultralow-k delamination of lead free-flip-chip packaging after TCT starts near the outermost bump, and then propagates simultaneously to the corner and the central area of the chip. Finite element simulation is employed to analyze the packaging stress distribution and the ultralow-k delamination mechanism. An underfill selection methodology is proposed to prevent ultralow-k delamination and lead-free solder bump cracks. In addition, an underfill experiment is carried out to confirm the finite element simulation result and verify the ultralow-k delamination mechanism.