Fractional-$N$ phase-locked loop frequency synthesizers based on time-to-digital converters (TDC-PLLs) have been proposed to reduce the area and linearity requirements of conventional PLLs based on delta-sigma modulation and charge pumps ($Delta Sigma$ -PLLs). Although TDC-PLLs with good performance have been demonstrated, TDC quantization noise has so far kept their phase noise and spurious tone performance below that of the best comparable $Delta Sigma$-PLLs. An alternative approach is to use a delta-sigma frequency-to-digital converter ( $Delta Sigma$ FDC) in place of a TDC to retain the benefits of TDC-PLLs and $Delta Sigma$-PLLs. This paper proposes a practical $Delta Sigma$ FDC based PLL in which the quantization noise is equivalent to that of a $Delta Sigma$ -PLL. It presents a linearized model of the PLL, design criteria to avoid spurious tones in the $Delta Sigma$ FDC quantization noise, and a design methodology for choosing the loop parameters in terms of standard PLL target specifications.