By Topic

Novel polysilicon sidewall gate silicon-on-sapphire MOSFET for power amplifier applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Johnson, R.A. ; California Univ., San Diego, La Jolla, CA, USA ; Kasa, S.D. ; de la Houssaye, P.R. ; Garcia, G.A.
more authors

We report the processing and DC and microwave characteristics of a novel thin-film silicon-on-sapphire MOS transistor which utilizes a sidewall process to realize a deep sub-micron gate length without the use of lithography. The device also incorporates an asymmetric lightly doped drain region for high breakdown voltage. Devices with 0.15 and 0.25 μm gate lengths have been fabricated. A FET with a 0.25 μm gate length and 1.0 μm LDD length had an ft=9 GHz, fmax=27 GHz and breakdown voltage of 13 volts

Published in:

SOI Conference, 1997. Proceedings., 1997 IEEE International

Date of Conference:

6-9 Oct 1997