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The interest in focal-plane processing techniques, by which image processing is carried out at pixel level, has increased since the advent of active pixel sensors in the middle 90's. By sharing processing circuitry by a group of neighboring pixels such techniques enable high-speed imaging operation and massive parallel computation. Focal-plane image compression is particularly interesting, because it allows for further reduction in data rates. The proposed approach also benefits from processing currents rather than voltages, which not only suits current-mode APS imagers, but also enables the circuits to operate at low voltage supply levels and achieve high speed. Moreover, arithmetic computations such as additions and scaling are easily implemented in current mode. Whereas current-mode imaging architectures produce higher fixed pattern noise (FPN) figures than their voltage-mode counterparts, low FPN can be achieved by applying correlated double sampling (CDS) and gain correction techniques. This work presents a 32 × 32 imaging integrated circuit that captures and compresses gray scale images on the focal plane of the image sensors using analog circuits that implement, for every 4 × 4 pixel block, differential pulse-code modulation, linear transform, and vector quantization. Other processing functions implemented in the chip are CDS, analog convolutions and A/D conversion. Theoretical details and circuit designs are described, as well as the test setup of the chip fabricated in a 0.35 μm CMOS process. Experimental results and photographs captured by the chip are shown to validate the technique. The CMOS imager compresses captured images at 0.94 bits/pixel for an overall power consumption below 40 mW (white image), which is equivalent to approximately 36 μW per pixel. Using photographs taken from bar-target pattern inputs, it is shown that details up to 2 cycles/cm are preserved in the decoded images.