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Standard cell libraries are designed focusing on the best performance-area trade-off for a technology at nominal supply. Scaling supply voltages emphasizes the effects of systematic or random variation. We revisit existing approaches and present two new design points in standard CMOS that target variability hardened standard cells integrated into the digital design flow. They are optimized for dynamic and stand-by power, respectively. A speed-up from 1.4 to more than 3x is achieved on cell level. These gains are preserved in the example of an FIR filter while even improving in energy efficiency. The analysis and design has been performed in a low-power 40nm CMOS technology.