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An efficient approach to pseudo-exhaustive test generation for BIST design

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2 Author(s)
C. -I. H. Chen ; Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA ; G. E. Sobelman

In the built-in self-test (BIST) methodology, the two major problems which must be addressed are test generation and response analysis. An efficient, unified solution to the problem of test generation is presented. A design procedure that is computationally efficient and produces test generation circuitry with low hardware overhead is proposed. The effectiveness of this approach is demonstrated by detailed comparisons of its results with those that would be obtained by existing techniques

Published in:

Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on

Date of Conference:

2-4 Oct 1989