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Scheduling unequal length tests in high performance VLSI system implementations

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2 Author(s)
Sayah, J. ; IBM, Hopewell Junction, NY, USA ; Kime, C.R.

Testing high-performance VLSI systems containing pipelines and multifunctional units is considered. An efficient heuristic-based algorithm is presented for scheduling tests in systems requiring unequal number of tests (UNT) for the test function. Performance results for an experimental implementation of the algorithm are presented

Published in:
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on

Date of Conference: 2-4 Oct 1989

Page(s):
566 - 570
Meeting Date :
02 Oct 1989-04 Oct 1989
Print ISBN:
0-8186-1971-6
INSPEC Accession Number:
3730560
Conference Location :
Cambridge, MA
Digital Object Identifier :
10.1109/ICCD.1989.63429
Product Type:
Conference Publications

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