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Maximal 13Bit Variable Resolution and Reducing Clipped Noise Flash ADC

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1 Author(s)
Xiangliang Jin ; Fac. of Mater., Optoelectron. & Phys., Xiangtan Univ., Xiangtan, China

An objective of this paper is to present the development progress of a high performance CMOS imager with one new analog to digital converter (ADC) scheme of maximal 13bit variable resolution and reducing the clipped noise. The response probability of human's eyes from dark to light is normal distribution in the region of [-1+σ, 1-σ]. In the interested region of human's eyes [-1+σ, 1-σ] there is a maximal 13bit resolution to improve the image quality and to save the power consumption and the chip size. The development being discussed uses an adjustable reference at both top and bottom of the non-uniformity series resistor of the variable resolution ADC to reduce the clipped noise and to provide the wide dynamic range benefits on CMOS imager chip. Based on reports coming out of industry and universities similar developments, this papers concerns about obtaining the high performance without increasing the circuit size and the chip power consumption. One UXGA CMOS sensor with the proposed ADC scheme is fabricated with 0.18um CMOS process. The test results show the improved image quality compared with the typical CMOS product with linear ADC. Test results show 79dB SNR (@Gain=0dB) with the power consumption of 90mW@54MHz.

Published in:

Engineering and Technology (S-CET), 2012 Spring Congress on

Date of Conference:

27-30 May 2012