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Simulation of MOS circuit performance degradation with emphasis on VLSI design-for-reliability

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2 Author(s)
Leblebici, Y. ; Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA ; Kang, S.M.

A framework for a reliability simulation tool to assess the hot-carrier-induced degradation of MOS circuits is presented, and the major components of this framework are examined. A method is introduced for dynamic simulation of hot-carrier-induced transistor degradation within the circuit environment. The approach accounts for the gradual degradation of terminal voltage waveforms of MOS transistors during long-term operation. It is demonstrated that the estimation of individual device lifetimes is not sufficient for circuit reliability assessment. The critical transistors that are most likely to cause circuit performance failures are identified by combining the long-term degradation estimates with the corresponding circuit performance sensitivities

Published in:

Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on

Date of Conference:

2-4 Oct 1989