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Design of Low Power On-chip Processor Arrays

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5 Author(s)
Lari, V. ; Dept. of Comput. Sci., Univ. of Erlangen-Nuremberg, Erlangen-Nuremberg, Germany ; Muddasani, S. ; Boppu, S. ; Hannig, F.
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In this paper, we present an ultra low power design for a class of massively parallel architectures, called tightly-coupled processor arrays.Here, the key idea is to exploit the benefits of a decentralized resource management as inherent to invasive computing for power saving.We propose concepts and studying different architecture trade-offs for hierarchical power management by temporarily shutting down regions of processors through power gating. Moreover, a) overall system chip energy consumption, b) hardware cost, and c) timing overheads are compared for different sizes of power domains.Experimental results show that up to 70,% of system energy consumption may be saved for selected characteristical algorithms and different resource utilizations.

Published in:

Application-Specific Systems, Architectures and Processors (ASAP), 2012 IEEE 23rd International Conference on

Date of Conference:

9-11 July 2012