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A Linear Algebra Core Design for Efficient Level-3 BLAS

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6 Author(s)
Pedram, A. ; Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA ; Gilani, S.Z. ; Nam Sung Kim ; Van De Geijn, R.
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Reducing power consumption and increasing efficiency is a key concern for many applications. It is well-accepted that specialization and heterogeneity are crucial strategies to improve both power and performance. Yet, how to design highly efficient processing elements while maintaining enough flexibility within a domain of applications is a fundamental question. In this paper, we present the design of a specialized Linear Algebra Core (LAC) for an important class of computational kernels, the level-3 Basic Linear Algebra Subprograms (BLAS). We demonstrate a detailed algorithm/architecture co-design for mapping a number of level-3 BLAS operations onto the LAC. Results show that our prototype LAC achieves a performance of around 64 GFLOPS (double precision) for these operations, while consuming less than 1.3 Watts in standard 45nm CMOS technology. This is on par with a full-custom design and up to 50× and 10× better in terms of power efficiency than CPUs and GPUs.

Published in:

Application-Specific Systems, Architectures and Processors (ASAP), 2012 IEEE 23rd International Conference on

Date of Conference:

9-11 July 2012