By Topic

A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Guohe Yin ; Institute of Microelectronics, Tsinghua University, Beijing, China ; He-Gong Wei ; U-Fat Chio ; Sai-Weng Sin
more authors

This paper presents a Successive Approximation Register Analog-to-Digital Converter (SAR ADC) design for sensor applications. An energy-saving switching technique is proposed to achieve ultra low power consumption. The measured Signal-to-Noise-and-Distortion Ratio (SNDR) of the ADC is 58.4 dB at 2 MS/s with an ultra-low power consumption of only 6.6 μW from a 0.8V supply, resulting in a Figure-Of-Merit (FOM) of 4.9 fJ/conversion-step. The prototype is fabricated in 65 nm CMOS technology with an area of 0.024 mm2.

Published in:

ESSCIRC (ESSCIRC), 2012 Proceedings of the

Date of Conference:

17-21 Sept. 2012