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A low-noise, 8.95–11GHz all-digital frequency synthesizer with a metastability-free time-to-digital converter and a sleepy counter in 65nm CMOS

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4 Author(s)
Chen Jiang ; Dept. of Microelectron., Fudan Univ., Shanghai, China ; Junren Liu ; Yumei Huang ; Zhiliang Hong

A low-noise 8.95~11GHz all digital frequency synthesizer (ADPLL) with a metastability-free first-order noise shaping time-to-digital converter (TDC) and a high frequency resolution digitally controlled oscillator (DCO) is presented. An input stage for TDC is proposed to solve the problem of metastability and a specific technique is used to power down the high speed counter as soon as the ADPLL is about to lock for power saving consideration. The ADPLL is fabricated in 65nm CMOS technology and the core area is 0.385mm2. With about 8.5μs locking time, the measured phase noise performance at 1MHz offset is -106.4dBc/Hz from a carrier of 10GHz. The ADPLL core consumes 17.52mW from a supply of 1V.

Published in:

ESSCIRC (ESSCIRC), 2012 Proceedings of the

Date of Conference:

17-21 Sept. 2012