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A Low-Power Compressive Sampling Time-Based Analog-to-Digital Converter

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6 Author(s)
Praveen K. Yenduri ; department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor ; Aaron Z. Rocca ; Aswin S. Rao ; Shahrzad Naraghi
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This paper presents a low-power, time-based, compressive sampling architecture for analog-to-digital conversion. A random pulse-position-modulation (PPM) analog-to-digital conversion (ADC) architecture is proposed. A prototype 9-bit random PPM ADC incorporating a pseudo-random sampling scheme is implemented as proof of concept. This approach leverages the energy efficiency of time-based processing. The use of sampling techniques that exploit signal compressibility leads to further improvements in efficiency. The random PPM (pulse-position-modulation) ADC employs compressive sampling techniques to efficiently sample at sub-Nyquist rates. The sub-sampled signal is recovered using a reconstruction algorithm, which is tailored for practical hardware implementation. We develop a theoretical analysis of the hardware architecture and the reconstruction algorithm. Measurements of a prototype random PPM ADC and simulation, demonstrate this theory. The prototype successfully demonstrates a 90% reduction in sampling rate compared to the Nyquist rate for input signals that are 3% sparse in frequency domain.

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IEEE Journal on Emerging and Selected Topics in Circuits and Systems  (Volume:2 ,  Issue: 3 )