By Topic

A 33-Megapixel 120-Frames-Per-Second 2.5-Watt CMOS Image Sensor With Column-Parallel Two-Stage Cyclic Analog-to-Digital Converters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

13 Author(s)

A 33-megapixel 120-frames/s (fps) CMOS image sensor has been developed. The 7808 × 4336 pixel 2.8-μm pixel pitch CMOS image sensor with 12-bit, column-parallel, two-stage, cyclic analog-to-digital converters (ADCs) and 96 parallel low-voltage differential signaling output ports operates at a data rate of 51.2 Gb/s. The pipelined operation of the two cyclic ADCs reduces the conversion time. This ADC architecture also effectively lowers the power consumption by exploiting the amplifier function of the cyclic ADC. The CMOS image sensor implemented with 0.18-μm technology exhibits a sensitivity of 0.76 V/lx·s without a microlens and a random noise of 5.1 erms- with no column amplifier gain and 3.0erms- with a gain of 7.5 at 120 fps while dissipating only 2.45 and 2.67 W, respectively.

Published in:

Electron Devices, IEEE Transactions on  (Volume:59 ,  Issue: 12 )