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The peaklike behavior of interface trap generation was observed in silicon-nanocrystal (Si-NC) memory during Fowler-Nordheim program/erase cycling. In addition to the two peaks at 0.3 and 0.85 eV from Pb0 centers, two extra peaks (0.45 and 0.7 eV) were also observed and suggested from Pb1 centers. In contrast, only Pb0 centers were observed in reference devices without Si-NCs. The result will be helpful to understand the effect of Si-NCs on the interface reliability.