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The XMOS Architecture and XS1 Chips

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1 Author(s)
May, D. ; Comput. Sci. Dept., Bristol Univ., Bristol, UK

The XMOS architecture scales from real-time systems with a single multithreaded processor to systems with thousands of processors. Concurrent processing, communications, and I/O are supported by the instruction set of the XCORE processors and by the message-routing techniques and protocols in the XMOS interconnect. The event-driven architecture supports energy-efficient multicore and multichip systems in which cores are active only when needed.

Published in:

Micro, IEEE  (Volume:32 ,  Issue: 6 )