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Cascaded two-level inverter-based multilevel static VAr compensator using 12-sided polygonal voltage space vector modulation

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2 Author(s)
N. N. V. Surendra Babu ; Department of Electrical Engineering, Indian Institute of Technology Bombay, Powai, Mumbai 400076, India ; B. G. Fernandes

A static VAr compensation scheme using 12-sided polygonal voltage space vectors for high power application is proposed in this study. Using the polygonal voltage space vectors, the dc bus utilisation is increased in linear modulation region and total harmonic distortion (THD) is improved significantly in over modulation region. The power circuit topology consists of two standard two-level inverters, which are connected in cascade through an open-ended winding transformer. In order to obtain the polygonal voltage space vectors, the dc-link voltage of inverter 2 is maintained at 0.366 times the dc-link voltage of inverter 1. A simple control strategy to maintain the required dc-link voltage ratio as well as for reactive power compensation is proposed. To verify the proposed strategy, simulation is carried in MATLAB/SIMULINK. Simulation study is performed in linear, over modulation regions of the inverter and also with unbalanced network voltages. A laboratory prototype is designed and developed to validate the simulation results. Further, this scheme is compared with a sinusoidal pulse width modulation-based VAr compensation scheme using the same topology.

Published in:

IET Power Electronics  (Volume:5 ,  Issue: 8 )