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A hierarchical power supply distribution model for full-chip switching noise analysis

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1 Author(s)
Chen, H.H. ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

This paper describes the use of a 12/spl times/12 SCM power supply distribution model, a 50/spl times/50 on-chip power bus model, and a distributed switching circuit model to analyze the on-chip power supply noise for high-performance VLSI design. The integrated model provides a complete analysis of the Vdd distribution, and allows designers to identify the hot spots on the chip and optimize design variables to minimize the noise.

Published in:

Electrical Performance of Electronic Packaging, 1997., IEEE 6th Topical Meeting on

Date of Conference:

27-29 Oct. 1997