By Topic

On the automatic integration of hardware accelerators into FPGA-based embedded systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Pilato, C. ; Dipt. di Elettron. ed Inf., Politec. di Milano, Milan, Italy ; Cazzaniga, A. ; Durelli, G. ; Otero, A.
more authors

This paper proposes an automatic framework for the seamless integration of hardware accelerators, starting from an OpenMP-based application and an XML file describing the HW/SW partitioning. It extends a fully software architecture by generating and integrating the cores, along with the proper interfaces, and the code for scheduling and synchronization. Experimental results show that it is possible to validate different solutions only by varying the input code.

Published in:

Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on

Date of Conference:

29-31 Aug. 2012