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On the automatic integration of hardware accelerators into FPGA-based embedded systems

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6 Author(s)
Pilato, C. ; Dipt. di Elettron. ed Inf., Politec. di Milano, Milan, Italy ; Cazzaniga, A. ; Durelli, G. ; Otero, A.
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This paper proposes an automatic framework for the seamless integration of hardware accelerators, starting from an OpenMP-based application and an XML file describing the HW/SW partitioning. It extends a fully software architecture by generating and integrating the cores, along with the proper interfaces, and the code for scheduling and synchronization. Experimental results show that it is possible to validate different solutions only by varying the input code.

Published in:

Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on

Date of Conference:

29-31 Aug. 2012

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