Skip to Main Content
This paper presents a work-in-progress design of a reconfigurable multi-processor architecture. The architecture is composed of nine nodes arranged in a 3x3mesh topology. The central node of the architecture hosts a RISC processor, which acts as master of the platform, taking care of data and task scheduling. The surrounding nodes hosts a reconfigurable engine and the actual processing. The system was prototyped on an Altera FPGA device and RTL simulations of the architecture were carried out to ensure the correct functionality of the systems. Future works will focus on the implementation of significant kernels of streaming applications on the platform as well as the implementation of power saving techniques in order to achieve a high power efficiency of the system.