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FPGA-based design and implementation of a multi-GBPS LDPC decoder

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2 Author(s)
Alexios Balatsoukas-Stimming ; Electronic and Computer Engineering Department, Technical University of Crete, 73100 Chania, Greece ; Apostolos Dollas

We design a very high speed LDPC code decoder architecture for (3,6)-regular codes by employing hybrid quantization, pipelining, and FPGA-specific optimizations. Our pipelined architecture fully addresses the decoder's significant I/O requirements, even when an early termination circuit is employed. The proposed decoder can achieve a throughput of up to 16.9 Gbps at an Eb/N0 of 3.5 dB using a code of length 1152, running at a clock speed of 153 MHz and performing a maximum of 10 decoding iterations, thus out-performing the state of the art by a significant margin. This design was fully implemented and tested on a Xilinx Virtex 5 XC5VLX110 FPGA. We also present an alternative, low-complexity design, which is able to achieve a throughput of up to 21.6 Gbps by sacrifing 0.75 dB in terms of Eb/N0.

Published in:

22nd International Conference on Field Programmable Logic and Applications (FPL)

Date of Conference:

29-31 Aug. 2012