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A CMOS standard three-stage ring oscillator is examined in UMC 0.13μm technology. The influence of PMOS transistors, as inverter feedbacks, on the ring oscillator performance is investigated. Since the ring oscillator usually drives a buffer in pulse generator/transmitter chain, dependence of its frequency and peak-to-peak amplitude on the buffer PMOS transistor feedback is presented in the paper. Simulation results showed that by varying the feedback transistor control voltage from 0 to Vdd, the ring oscillating frequency can be controlled in the range of 3.15 GHz in the three PMOS transistor feedbacks topology, 2.3 GHz in the two feedbacks architecture, 0.95 GHz (the best case) in the one feedback ring oscillator designs, and 1.5 GHz for the PMOS transistor feedback used in the buffer stage. Moreover, the maximum frequency of 8.9 GHz obtained in the latter case is significantly higher than 7.65 GHz achieved without any feedback.