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A Switcher ASIC Design for Use in a Charge-Pump Detector

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6 Author(s)
Zhi Yong Li ; Department of Electrical and Computer Engineering, New Jersey Institute of Technology, NJ, USA ; Gianluigi De Geronimo ; D. Peter Siddons ; Durgamadhab Misra
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The objective of this paper is to describe a Switcher ASIC with 64 high voltage output channels. Each channel provides two high voltage control pulses with maximum amplitudes of 32 V. The high voltage level shifter was designed with a current mirror switching circuit that has a readily adjustable switching speed, unlike conventional switching circuits. The logic control circuit uses a forward and reverse chain of Flip-Flops along with other combinational logic gates to generate bidirection sequential control pulses with adjustable pulsewidth and polarity. The layout was carefully designed to achieve a 14 μ m width for the last stage transistors' drain path based on the 50 μm output channel pitch set up. At least a 200 mA current driving capability was obtained for each channel. The design was fabricated using TSMC's 180 nm CMOS HV technology. The paper further discusses the critical design steps including chip architecture, layout, simulation and bench test. The final experimental results demonstrate that the Switcher ASIC meets requirements and the rising time could reach 480 ns with a 1 nF capacitive load at 15 V pulse amplitude. With this load, the total power consumption of the chip was measured to be approximately 4 mW when the input clock period was 42.2 μs. In addition to use in a charge-pump detector, the ASIC can be used to control the charge accumulation and readout in other detectors, such as X-ray pump probe detectors (XPP).

Published in:

IEEE Transactions on Nuclear Science  (Volume:59 ,  Issue: 6 )